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TC90A58F
Preliminary
TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic
TC90A58F
3-Channel AD Converter
The TC90A58F is a 3-channel AD converter for video applications which incorporates a clamp circuit. The 10-bit converter can be used as either an 8-bit 3-channel AD converter or as a 10-bit 2-channel AD converter.
Main Functions and Features
* * * * * * * * * * * * 3-channel, 8-bit AD converter (input amplitude: 1.32 Vp-p) Y, Cb and Cr or R, G and B inputs. Pedestal clamp (Y or RGB: 16 LSB (in 8-bit conversion), Cb, Cr: 128 LSB (in 8-bit conversion) Switchable between external input or internal generation of clamp pulse Operates at 30 MHz maximum. Digital filter (Y: 6 MHz, Cb, Cr: 2.8 MHz/6 MHz) 10-bit output (only for 2-channel ADC) Horizontal PLL (HPLL) ITU-R601 and ITU-R656 formats supported (For ITU-R656, HD and VD must be input.) Y-signal delay circuit (delay amount can be set from 0 to 14 clocks, in units of clocks) I2C bus control Built-in color bar generator Weight: g (typ.)
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Block Diagram
VB1 VREF DACOUT
DAC for ADC Test VRT_Y AIN_Y VRB_Y Y 8 Cb Delay & Format 10 Cb/Cr 8 Cb/Cr or Cb GOUT[7:0] 8 VRT_Q AIN_Q VRB_Q BIAS ADCLAMP RESN Cr ADC 10 Digital Filters VDOUT HDOUT Sync/Clamp Pulse Generator APCLK HPLL I C Bus
2
Y ADC 10
CCIR601/656 Format
Y/Cb/Cr or Y ROUT[7:0] 8
VRT_I AIN_I VRB_I
Cb ADC 10
BOUT[7:0] 8
CLAMP HDIN
VDIN
HREF CKSEL[3:0] EXTCLK BFIL
LFIL TES[2:0]
SCK
SDA
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Pin Description
TES1 TES2 CLAMP RESN CKSEL0 CKSEL1 CKSEL2 CKSEL3 RREF VRT_Y AVSS AIN_Y AVDD VRB_Y VRM_Y DVSSA DVDDA DVSS
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
BIAS VRM_I VRB_I AVDD AIN_I AVSS VRT_I DACOUT VB1 VRM_Q VRB_Q AVDD AIN_Q AVSS VRT_Q PVDD APCLK PVSS LFIL BFIL
DVDD
TES0
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
TC90A58F
60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41
ROUT7 ROUT6 ROUT5 ROUT4 ROUT3 ROUT2 ROUT1 ROUT0 DVSS GOUT7 GOUT6 GOUT5 GOUT4 GOUT3 GOUT2 GOUT1 GOUT0 DVSS CKOUT DVDD
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 DVDDP EXTCLK DVSSP HDIN VDIN HREF SDA SCL VDOUT HDOUT DVDD DVSS BOUT0 BOUT1 BOUT2 BOUT3 BOUT4 BOUT5 BOUT6 BOUT7
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Pin Functions
No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Pin Name BIAS VRM_I VRB_I AVDD AIN_I AVSS VRT_I DACOUT VB1 VRM_Q VRB_Q AVDD AIN_Q AVSS VRT_Q PVDD I/O O O O 3/4 I 3/4 O O 3/4 O O 3/4 I 3/4 O 3/4 Function Bias pin (for AD) AD reference voltage (middle) AD reference voltage (bottom) Analog power supply AD input Analog GND AD reference voltage (top) Analog pin (for testing) Analog pin (for testing) AD reference voltage (middle) AD reference voltage (bottom) Analog power supply AD input Analog GND AD reference voltage (top) HPLL power supply Notes Ground to AVSS (pin 6) via 0.1-mF capacitor. Same as above Same as above 3/4 Connect 0.47-mF capacitor and 20-W resistor. 3/4 Ground to AVSS (pin 6) via 0.1-mF capacitor. For testing purposes Ground to AVSS (pin 14) via 0.1-mF capacitor. Ground to AVSS (pin 14) via 0.1-mF capacitor. Ground to AVSS (pin 14) via 0.1-mF capacitor. 3/4 Connect 0.47-mF capacitor and 20-W resistor. 3/4 Ground to AVSS (pin 14) via 0.1-mF capacitor. 3/4 Outputs clock with amplitude of 1 Vp-p according to corresponding I2C bus register setting. 17 APCLK O Clock output When I C bus register settings are default values, outputs are fixed to L. 18 PVSS 3/4 HPLL GND 3/4 Connecta 1-mF capacitor and a 1.0-kW resistor. 19 LFIL 3/4 HPLL filter Connect other end of capacitor as near to PVSS as possible. Also connect 0.01-mF capacitor in parallel with above capacitor and resistor. Connect 0.01-mF capacitor. For HPLL Used as clock input pin in External Clock Mode. 22 23 24 25 26 27 28 29 EXTCLK DVSSP HDIN VDIN HREF SDA SCL VDOUT I 3/4 I I I I/O I O External clock input When built-in HPLL is used, set input to H or fix input to L. Digital GND HD input VD input HPLL pin Phase is compared on rising edge. I C bus data I C bus clock VD output
2 2 2
20 21
BFIL DVDDP
3/4 3/4
For stabilization Digital power supply
For HPLL 5-V withstanding voltage 5-V withstanding voltage Input for external HPLL reference signal
5-V withstanding voltage 5-V withstanding voltage Outputs vertical sync signal pulse. Pulse polarity can be set using I C bus register. Outputs horizontal sync signal pulse.
2
30 31 32 33 34 35
HDOUT DVDD DVSS BOUT0 BOUT1 BOUT2
O 3/4 3/4 O O O
HD output Digital power supply Digital GND -/B/-OUTPUT -/B/-OUTPUT -/B/-OUTPUT Internal, for output PAD Internal, for output PAD
Pulse polarity can be set using I C bus register.
2
3/4 3/4 3/4
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No. 36 37 38 39 40 41 Pin Name BOUT3 BOUT4 BOUT5 BOUT6 BOUT7 DVDD I/O O O O O O 3/4 Function -/B/-OUTPUT -/B/-OUTPUT -/B/-OUTPUT -/B/-OUTPUT -/B/-OUTPUT Digital power supply Internal, for output PAD Outputs internally-oscillated or externally-input clock. 42 CKOUT O Clock output Polarity controllable using I C bus register. Clock output can be stopped using I C bus register. When clock output is halted, output goes High-Impedance. 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 DVSS GOUT0 GOUT1 GOUT2 GOUT3 GOUT4 GOUT5 GOUT6 GOUT7 DVSS ROUT0 ROUT1 ROUT2 ROUT3 ROUT4 ROUT5 ROUT6 ROUT7 DVDD DVSS DVDDA DVSSA VRM_Y VRB_Y AVDD AIN_Y AVSS VRT_Y RREF 3/4 O O O O O O O O 3/4 O O O O O O O O 3/4 3/4 3/4 3/4 O O 3/4 I 3/4 O I Digital GND C/G/-output C/G/-output C/G/-output C/G/-output C/G/-output C/G/-output C/G/-output C/G/-output Digital GND Y/R/BS output Y/R/BS output Y/R/BS output Y/R/BS output Y/R/BS output Y/R/BS output Y/R/BS output Y/R/BS output Digital power supply Digital GND Digital power supply Digital GND AD reference voltage (middle) AD reference voltage (bottom) Analog power supply AD input Analog GND AD reference voltage (top) Reference resistance Connect other end of resistor to analog power supply. Internal, for output PAD Internal, for output PAD For AD digital block For AD digital block Ground to AVSS (pin 69) via 0.1-mF capacitor. Ground to AVSS (pin 69) via 0.1-mF capacitor. 3/4 Connect 0.47-mF capacitor and 20-W resistor. 3/4 Ground to AVSS (pin 69) via 0.1-mF capacitor. AD reference resistance: Connect 8.2-kW resistor. Internal, for output PAD 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4
2 2
Notes 3/4 3/4 3/4 3/4 3/4
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No. 72 73 74 75 76 Pin Name CKSEL3 CKSEL2 CKSEL1 CKSEL0 RESN I/O I I I I I Clock select Clock select Clock select Clock select Reset pin Function Notes Sets relationship between input H frequency and HPLL oscillation frequency. Also switches between internal oscillation frequency and external 2 clock input. When selecting clock using I C bus register, set CKSEL to all L. H for normal operation, L for reset Input for ADC clamp signal. Polarity can be changed using I C bus register. By default, clamp is applied by H. 77 CLAMP I Clamp pin Switches between external input / internal generation of clamp 2 signal according to I C Bus Register setting. Set to L. TES1 and TES0 determine 2 least significant bits of I C bus control slave address (details are given later).
2 2
78 79 80
TES2 TES1 TES0
I I I
For testing purposes For testing purposes For testing purposes
Functions
1. Low-Pass Filter (LPF)
TC90A58F incorporates a low-pass filter (-3dB) for Y and C signals. When the system clock is 27 MHz, cut-off frequency is 6 MHz for Y signal and 2.8 MHz for C signal. When the system clock frequency is higher than 27 MHz, cut-off frequencies are determined as follows: Example: System clock frequency = 29.82 MHz Y signal cut-off frequency: 6 (MHz) (29.82 (MHz) 27 (MHz)) = approx. 6.63 MHz Cb, Cr cut-off frequency: 2.8 (MHz) (29.82 (MHz) 27 (MHz)) = approx. 3.09 MHz Low-pass filter characteristic for Y and C signals is shown below:
Y (RGB) Signal Cut-off Frequency = 6 MHz
WAFP for DOS/V V1.3 [amp: dB] 5 0 -5 -10 -15 -20 -25 -30 -35 -40 -45 -50 -55 -60 -65 -70 -75 0 (DC offset: -0.26) 2M *** copyright 1993, 94 by TOSHIBA [AVL] *** CONV. TIM May 10 1999
4M
6M
8M
10M
12M [freq: Hz]
Figure 1 Y Signal LPF Characteristic (system clock = 27 MHz)
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Cb, Cr Signal Cut-off Frequency = 2.8 MHz
WAFP for DOS/V V1.3 [amp: dB] 5 0 -5 -10 -15 -20 -25 -30 -35 -40 -45 -50 -55 -60 -65 -70 -75 0 (DC offset: 0.00) 2M *** copyright 1993, 94 by TOSHIBA [AVL] *** CONV. TIM May 10 1999
4M
6M
8M
10M
12M [freq: Hz]
Figure 2 C Signal LPF Characteristic (system clock = 27 MHz)
2. Output Format Setting
Eight output formats are supported as detailed below. Set the output format in the bits MODE2~MODE0 of the I2C bus register Sub-Address 00H. (1) Output format in Standard 4:2:2 Mode
Y07-0 Cb07-0 Y17-0 Cr17-0 Y27-0 Cb27-0 Y37-0 Cr27-0 Hi-Z Y47-0 Cb47-0 Y57-0 Cr47-0 Y67-0 Cb67-0 Y77-0 Cr67-0
ROUT[7:0] GOUT[7:0] BOUT[7:0]
(2)
Output format in Special 4:2:2 Mode
Y07-0 Cb07-0 Y17-0 Cr17-0 Y27-0 Cb27-0 Y37-0 Cr37-0 Hi-Z Y47-0 Cb47-0 Y57-0 Cr57-0 Y67-0 Cb67-0 Y77-0 Cr77-0
ROUT[7:0] GOUT[7:0] BOUT[7:0]
(3)
Output format in 4:4:4 Mode
Y07-0 Cb07-0 Cr07-0 Y17-0 Cb17-0 Cr17-0 Y27-0 Cb27-0 Cr27-0 Y37-0 Cb37-0 Cr37-0 Y47-0 Cb47-0 Cr47-0 Y57-0 Cb57-0 Cr57-0 Y67-0 Cb67-0 Cr67-0 Y77-0 Cb77-0 Cr77-0
ROUT[7:0] GOUT[7:0] BOUT[7:0]
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(4) Output format in Standard 4:4:1 Mode
ROUT[7:0] GOUT[7:6] GOUT[5:4] GOUT[3:0] BOUT[7] BOUT[6:0] Y07-0 Cb07-6 Cr07-6 Y17-0 Cb05-4 Cr05-4 Y27-0 Cb03-2 Cr03-2 Y37-0 Cb01-0 Cr01-0 Hi-Z TRG Hi-Z Y47-0 Cb47-6 Cr47-6 Y57-0 Cb45-4 Cr45-4 Y67-0 Cb43-2 Cr43-2
(5)
Output format in Special 4:1:1 Mode
ROUT[7:0] GOUT[7:6] GOUT[5:4] GOUT[3:0] BOUT[7] BOUT[6:0] Y07-0 Cb03-2 Cb01-0 Y17-0 Cb07-6 Cb05-4 Y27-0 Cr23-2 Cr21-0 Y37-0 Cr27-6 Cr25-4 Hi-Z TRG Hi-Z Y47-0 Cb43-2 Cb41-0 Y57-0 Cb47-6 Cb45-4 Y67-0 Cb63-2 Cb61-0
Note1: In the above format, 1-data cycle is the main clock (MCK). (For example, when the clock generated by HPLL is 29.82 MHz, MCK = 29.82 MHz)
(6)
Output format in ITU-R601 16-Bit Mode (data rate: 13.5 MHz)
Y07-0 Cb07-0 Y17-0 Cr07-0 Y27-0 Cb27-0 Y37-0 Cr27-0 Hi-Z Y47-0 Cb47-0 Y57-0 Cr47-0 Y67-0 Cb67-0 Y77-0 Cr67-0
ROUT[7:0] GOUT[7:0] BOUT[7:0]
(7)
Output format in ITU-R601 8-Bit Mode (data rate: 27 MHz)
Cb07-0 Y07-0 Cr07-0 Y17-0 Hi-Z Hi-Z Cb27-0 Y27-0 Cr27-0 Y37-0
ROUT[7:0] GOUT[7:0] BOUT[7:0]
(8)
ITU-R656 Adds SAV and EAV (H, V and F information) to the data in format 7 and outputs the result.
3. Y Signal Delay Circuit
The circuit can delay the Y signal by 0 to 14 clocks in relation to the C signal. The delay can be set in the bits YDLY3~YDLY0 of the I2C bus register Sub-Address 17H.
4. Color Bar Generator
Color bars for both NTSC and PAL can only be generated internally in ITU-R656 or ITU-R601 (either 8- or 16-bit) Mode. The color bar mode can be set in the BAR bit of the I2C bus register Sub-Address 2AH.
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5. HD Output
The output timing and width of HDOUT (pin 30) can be set in the I2C bus registers (see figure below). Timing: HDSTA10~HDSTA5 in Sub-Address 05H and HDSTA4~HDSTA0 in Sub-Address 06H Output width: HDPW10~HDPW8 in Sub-Address 06H and HDPW7~HDPW0 in Sub-Address 07H
HD (INPUT) MCK (APCLK) (29.862 MHz) HDOUT HD output width 2 (set in I C bus register) HD output timing 2 (set in I C bus register)
Figure 3 HDOUT Timing Chart
The HD signal input from the HDIN (pin 24) can pass through unaltered and be output from HDOUT. In this case, the HDOUT output is delayed by 15 clocks from the HDIN input. Through Mode can be set using the HDSELB bit in the I2C bus register Sub-Address 00H.
6. VD Output
The VD signal output from the VDIN (pin 24) can pass through unaltered and be output from VDOUT (pin 29). There are two output timings: output delayed by 15 clocks from VDIN or output at the same timing as HDOUT. The timing can be selected in the I2C bus register VDOSEL Sub-Address 09H. The VD signal can also be generated internally. Select internal generation using the VRNMOD bit in the I2C bus register Sub-Address 02H.
Odd field 1/2H VD (INPUT, odd field) Within 15 clocks HD (INPUT)
MCK (APCLK) (29.862 MHz) HDOUT Variable (set using I C bus register) VDOUT When VDSEL = 0, VDSOFF = 0 and VRNMOD = 0, VD input from VDIN is output, delayed by 15 clocks. With all other settings, VDOUT changes with the same timing as HDOUT.
2
Variable (set using I C bus register)
2
Figure 4 VDOUT Timing Chart
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7. Multiplexing H, V and F
In ITU-R656 Mode only, SAV and EAV (H, V and F information) are multiplexed in the data. Where data is multiplexed depends on the HD output timing.
8. I C Bus
The TC90A58F bus control format conforms to the Philips I2C bus control format. The two least significant bits (A0 and A1) of the slave address can be set using TES1 and TES0 (pins 79 and 80).
2
Slave Address
A6 1 A5 0 A4 0 A3 1 A2 1 A1 A1 A0 A0 R/W 3/4
Set two least significant bits (A0 and A1).
TES1 0 0 1 1
TES0 0 1 0 1
Slave Address 10011000 10011010 10011100 10011110
9. Countermeasure against HDIN and VDIN Pulse Noise (to avoid misinterpretation)
A countermeasure is taken to prevent spike noise in the pulse input to the HDIN and VDIN pins from being misinterpreted as genuine HD and VD input. The noise-detection width (either all pulses of less than 8 clocks or all pulses of less than 1 clock are regarded as noise) can be set using the bits HDDIRECT and VDDIRECT in the I2C bus registers Sub-Address 03H.
10. Countermeasure against VDIN Noise (to avoid misinterpretation)
A countermeasure is taken to prevent noise in 1 V (during vertical scanning) from being misinterpreted as VD. Noise rejection can be switched ON/OFF using the VGATEON bit in the I2C bus register Sub-Address 11H. The noise detection range can be set using the VGTEGA and VGTEGB bits in Sub-Address 0FH~ Sub-Address 11H).
11. Internal Generation of Clamp Pulse
The clamp pulse can be internally generated. Switching between external input and internal generation of the clamp pulse can be set using the CLPSEL bit in the I2C bus register Sub-Address 0EH. The clamp pulse generation timing and width can be set using the corresponding I2C bus registers. Timing: CLPSTA10~CLPSTA4 in Sub-Address 0CH and CLPSTA3~CLPSTA0 in Sub-Address 0DH Pulse width: CLPWID10~CLPWID7 in Sub-Address 0DH and CLPWID6~CLPWID0 in Sub-Address 0EH
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12. Built-in HPLL
The TC90A58F has a built-in horizontal PLL. The following parameters can be set using the I2C bus registers. * Divider control (when using internal divider): DIVIIC3~DIVIIC0 in Sub-Address 14H Can also be set using CKSEL[3:0] (pins 72~75) as well as in the I2C bus register. CKSEL[3:0] is enabled only when DIVIIC3~DIVIIC0 in is all 0s. * Selection of phase comparator (PC) in HPLL (PC2 or PC3): PCSEL0~PCSEL1 in Sub-Address 01H * Selection of divider (internal or external): DIVSEL in Sub-Address 01H * 1-Vp-p output / full-swing output (APCLK output): OUTSEL in Sub-Address 01H * HPLL oscillation/oscillation halt: HPLLSTOP in Sub-Address 01H
HREF
2 DIVN HDIV DIVSEL (div: 1896/948/880/660) (ECL PC3 PCSEL Gyrator type VCO1
OUTSEL TEST 1-Vp-p sine wave Full-scale square wave APCLK
BUFFER
(29.82 MHz/29.82 MHz/ 29.7 MHz/29.7 MHz)
(15.75/31.5/ 33/45 kHz) HD VD V mask Dedicated Dedicated VDD VSS PC2 IFIL
AGC AGCOFF BFIL
AVDD
AVSS
Figure 5 Block Diagram of HPLL 13. 10-Bit ADC
The TC90A58F can also be used as a 10-bit AD converter. This setting can be made using the M10B bit in the I2C bus register Sub-Address 1CH. Note that when the device is used as a 10-bit AD converter, only two channels (the Y and Cb signals) are output from the following output pins. Y signal: ROUT[7:0], GOUT[7:6] Cb signal: GOUT[1:0], BOUT[7:0] When the TC90A58F is used as a 10-bit AD converter, only certain functions can be used. Available functions 1. Low-pass filter 2. Output format setting (4:4:4 only) 3. Y delay (Y signal only) 4. Color bar generation (4:4:4 only) 5. HDOUT timing adjustment 6. VDOUT timing adjustment 8. I2C bus register setting 9. Countermeasure against HDIN and VDIN pulse noise 10. Countermeasure against VDIN noise 11. Clamp pulse timing 12. HPLL settings 14. Clamp level setting Unavailable functions Processing for R601, R656, 4:1:1 and 4:2:2 modes (for functions 2, 4 and 7 in the list of available functions shown above)
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14. Clamp Level
The clamp level is set to the following values: Y (RGB): 16 (for 8-bit conversion) C: 128 (for 8-bit conversion)
15. ADC Input Signal
The input signal band and range are as follows: Band: 10 MHz Range: 1.32 Vp-p (typ.), 0.99 Vp-p~2.31 Vp-p
16. 5-V Withstanding Voltage
HDIN, VDIN, SDA and SCL (pins 24, 25, 27 and 28) have a withstanding voltage of 5 V.
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I C Bus Register Map
1. Format
The TC90A58F bus control format conforms to the Philips I2C bus control format standard.
2
Data transfer format
S Slave address 7 bits MSB MSB 0A Sub-address 8 bits MSB A Data 8 bits AP
S: Start condition P: Stop condition A: Acknowledgement (1) Start and stop conditions
SDA
SCL S Start condition P Stop condition
(2)
Bit transfer
SDA
SCL
SDA must not be changed.
SDA may be changed.
(3)
Acknowledgement
SDA from master
SDA from slave
High-Impedance
SCL from master 1 S 8 9
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(4)
A6 1
Slave address
A5 0 A4 0 A3 1 A2 1 A1 A1 A0 A0 R/W 3/4
Note2: A1 and A0 are set using pins 79 and 80. Purchase of TOSHIBA I2C components conveys a license under the Philips I2C Patent Right to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips.
2. Settings
Sub-Address (H) 00 01 02 03 04 05 06 07 08 09 0C 0D 0E 0F 10 11 12 13 14 17 18 19 1A 1B 1C 2A MSB Bit 7 * * DAPWDN HVSEL656 HRTMG9 HRTMG1 HDSTA4 HDPW7 IHVD VRTMG2 ADCLAPO CLPSTA3 CLPWID6 * VGTEDA4 VGTEDB6 * ODEV3 DIVIIC3 REG4 REG11 REG9 REG12 REGSWR7 M10B * Bit 6 NTPAL PCSEL0 ADPWDN INTER HRTMG8 HRTMG0 HDSTA3 HDPW6 VRTMG9 VRTMG1 CLPSTA10 CLPSTA2 CLPWID5 * VGTEDA3 VGTEDB5 ODEV10 ODEV2 DIVIIC2 REG5 LPFYPASS REG7 * REGSWR1 * * Bit 5 MODE2 PCSEL1 VRNMOD VNSOFF HRTMG7 HDSTA10 HDSTA2 HDPW5 VRTMG8 VRTMG0 CLPSTA9 CLPSTA1 CLPWID4 * VGTEDA2 VGTEDB4 ODEV9 ODEV1 DIVIIC1 REG6 LPI0ON2 REG8 * REGSWG7 * * Bit 4 MODE1 DIVSEL VCNTCR VDPO HRTMG6 HDSTA9 HDSTA1 HDPW4 VRTMG7 VDOSELGT CLPSTA8 CLPSTA0 CLPWID3 VGTEDA9 VGTEDA1 VGTEDB3 ODEV8 ODEV0 DIVIIC0 REG10 LPI0ON1 QDSEL1 * REGSWG3 CKOUTSTP * Bit 3 MODE0 VCOAGC HDPQO VDDIRECT HRTMG5 HDSTA8 HDSTA0 HDPW3 VRTMG6 VDOSEL CLPSTA7 CLPWID10 CLPWID2 VGTEDA8 VGTEDA0 VGTEDB2 ODEV7 ODDETPO DIVHDSEL YDLY3 LPI0ON0 QDSEL0 * REGSWG1 * * Bit 2 RGBC OUTSEL VDPQO HDPO HRTMG4 HDSTA7 HDPW10 HDPW2 VRTMG5 VGSTA CLPSTA6 CLPWID9 CLPWID1 VGTEDA7 VGTEDB9 VGTEDB1 ODEV6 * HRESVAR YDLY2 LPQ0ON2 IDSEL1 * REGSWB7 * * Bit 1 VLINSEL CLKSEL HDPOL HDDIRECT HRTMG3 HDSTA6 HDPW9 HDPW1 VRTMG4 REGF1 CLPSTA5 CLPWID8 CLPWID0 VGTEDA6 VGTEDB8 VGTEDB0 ODEV5 * * YDLY1 LPQ0ON1 IDSEL0 * REGSWB6 * BAR LSB Bit 0 HDSELB CKPOL * HRTMG10 HRTMG2 HDSTA5 HDPW8 HDPW0 VRTMG3 REGF2 CLPSTA4 CLPWID7 CLPSEL VGTEDA5 VGTEDB7 VGATEON ODEV4 * * YDLY0 LPQ0ON0 LPYON * REGSWHV * *
Note3: * indicates that use is prohibited. Set to L.
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3. Settings in Detail Sub-Address 00H
Bit Name Default 7 (MSB) 3/4 3/4 6 NTPAL 0 5 MODE2 0 4 MODE1 0 3 MODE0 0 2 RGBC 0 1 VLINSEL 0 0 (LSB) HDSELB 0
*
NTPAL: Switches between NTSC and PAL. 0 (default): NTSC 1: PAL
*
MODE2~MODE0: Switches output format.
MODE2 0 0 0 0 1 1 1 1
MODE1 0 0 1 1 0 0 1 1
MODE0 0 1 0 1 0 1 0 1
Output Format 4:2:2 (standard, default) 4:2:2 (special) 4:1:1 (standard) 4:1:1 (special) 4:4:4 R601 16-Bit Mode R601 8-Bit Mode R656
*
RGBC: Switches the ADC clamp level for Cb and Cr. 0 (default): The ADC clamp level is 16 LSB for Y (for 8-bit conversion) and 128 LSB for Cb and Cr (for 8-bit conversion). The clamp level is the pedestal clamp. 1: The clamp level for Y, Cb and Cr is 16 LSB (for 8-bit conversion) (for RGB) The clamp level is the pedestal clamp.
*
VLINSEL: Sets the number of vertical lines. 0 (default): 525 (when NTPAL = 0) or 625 (when NTPAL = 1) 1: Any value from 1 to 1023 (Set using bits VLIN9~VLIN0 in Sub-Addresses 08H and 09H.)
*
HDSELB: Switches HD output signal. 0 (default): Variable HD output timing 1: Fixed HD output timing
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Sub-Address 01H
Bit Name Default 7 (MSB) 3/4 3/4 6 PCSEL0 0 5 PCSEL1 0 4 DIVSEL 0 3 HPLLSTOP 0 2 OUTSEL 0 1 CLKSEL 0 0 (LSB) CKPOL 0
*
PSCEL0~PSCEL1
Switches the phase comparator in HPLL.
PCSEL0 0 1 0 1
PCSEL1 0 0 1 1
PC Used PC2 (default) Use prohibited Use prohibited PC3
*
DIVSEL: Switches the reference HD. 0 (default): the Reference HD generated internally 1: Reference HD input externally (via HREF pin)
*
HPLLSTOP: Switches HPLL oscillation ON/OFF. 0 (default): HPLL oscillates. 1: HPLL stops oscillating.
*
OUTSEL: Switches the clock (APCLK) output. 0 (default): Full-swing (square) output 1: 1-Vp-p output
*
CLKSEL: Switches the clock. 0 (default): Uses clock generated by HPLL. 1: Uses clock input externally.
*
CKPOL: Switches the polarity of output clock (APCLK and CKOUT). 0 (default): Positive polarity 1: Negative polarity
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Sub-Address 02H
Bit Name Default 7 (MSB) DAPWDN 0 6 ADPWDN 1 5 VRNMOD 0 4 VCNTCR 0 3 HDPQO 0 2 VDPQO 0 1 HDPOL 0 0 (LSB) 3/4 3/4
*
DAPWDN: DAC power-down ON/OFF 0 (default): DAC power-down ON 1: DAC power-down OFF
*
ADPW: ADC power-down ON/OFF 0: ADC power-down ON 1 (default): ADC power-down OFF
*
VRNMOD: Used to set the VD output timing before the VD input timing. 0 (default): VD outputs VD input signal. 1: Because the VD signal is generated internally, the VD output timing can be before the VD input timing.
*
VCNTCR: Sets the V counter reset timing. 0 (default): Resets at H counter = 0. 1: Reset on falling edge of HDOUT
*
HDPOQ: Switches the HD output polarity. 0 (default): Negative polarity (HDOTD = 0), same polarity as the input HD (HDSELB = 1 and HDPO = 0), or opposite polarity from the input HD (HDSELB = 1 and HDPO = 1) 1: Positive polarity (HDOTD = 0), opposite polarity from the input HD (HDSELB = 1 and HDPO = 0), or same polarity as the input HD (HDSELB = 1 and HDPO = 1)
*
VDPOQ: Switches the VD output polarity. 0 (default): Negative polarity (VNSOFF = 1 or VRNMOD = 1), same polarity as the input VD (VNSOFF = 0, VRNMOD = 0 and VDPO = 0), or opposite polarity from the input VD (VNSOFF = 0, VRNMOD = 0 and VDPO = 1) 1: Positive polarity (VNSOFF = 1 or VRNMOD = 1), opposite polarity from the input VD (VNSOFF = 0, VRNMOD = 0 and VDPO = 0), or same polarity as the input VD (VNSOFF = 0, VRNMOD = 0 and VDPO = 1)
*
HDPOL: Switches the HPLL HD input polarity. 0 (default): Same polarity as the input HD 1: Opposite polarity from the input HD
17
2002-02-06
TC90A58F
Sub-Address 03H
Bit Name Default 7 (MSB) HVSEL65 0 6 INTER 0 5 VNSOFF 0 4 VDPO 0 3 VDDIRECT 0 2 HDPO 0 1 HDDIRECT 0 0 (LSB) HRTMG10 1
*
HVSEL65: Changes the HD and VD output timing in relation to EAV. 0 (default): HD and VD output timing is the same as EAV. 1: HD and VD output timing is delayed in relation to EAV by +32 clocks for NTSC and by +24 clocks for PAL.
*
INTER: Sets the VD output to be once or twice per frame (Note4). (Enabled only when VRNMOD = 1) 0 (default): Outputs VD for each field. 1: Outputs VD per frame. Note4: A frame consists of 525 lines for NTSC; 625 lines for PAL.
*
VNSOFF: Enables/Disables VD input. 0 (default): Enables VD input. 1: Disables VD input.
*
VDPO: Sets the VD input polarity. 0 (default): Same polarity 1: Opposite polarity
*
VDDIRECT: Selects VD input. 0 (default): Identifies input pulses of 8 clocks or more as VD input. 1: Identifies input pulses of 1 clock or more as VD input.
*
HDPO: Sets the HD input polarity. 0 (default): Same polarity 1: Opposite polarity
*
HDDIRECT: Selects HD input. 0 (default): Identifies input pulses of 8 clocks or more as HD input. 1: Identifies input pulses of 1 clock or more as HD input.
*
HRTMG10: Sets the number of samples per 1H. Sets in combination with HRTMG9~HRTMG2 in Sub-Address 04H and HRTMG1~HRTMG0 in Sub-Address 05H.
Sub-Address 04H
Bit Name Default 7 (MSB) HRTMG9 1 6 HRTMG8 0 5 HRTMG7 1 4 HRTMG6 0 3 HRTMG5 1 2 HRTMG4 1 1 HRTMG3 0 0 (LSB) HRTMG2 0
*
HRTMG9~HRTMG2: Sets the number of samples per 1H. This setting works in combination with HRTMG10 in Sub-Address 03H and HRTMG1~HRTMG0 in Sub-Address 05H.
18
2002-02-06
TC90A58F
Sub-Address 05H
Bit Name Default 7 (MSB) HRTMG1 1 6 HRTMG0 1 5 HDSTA10 0 4 HDSTA9 0 3 HDSTA8 0 2 HDSTA7 0 1 HDSTA6 0 0 (LSB) HDSTA5 0
*
HRTMG1~HRTMG0: Sets the number of samples per 1H. This setting works in combination with the settings of HRTMG10 in Sub-Address 03H and HRTMG9~HRTMG2 in Sub-Address 04H. HDSTA10~HDSTA5: Sets the HD output timing. This setting works in combination with the setting of HDSTA4~HDSTA0 in Sub-Address 06H.
*
Sub-Address 06H
Bit Name Default 7 (MSB) HDSTA4 1 6 HDSTA3 0 5 HDSTA2 0 4 HDSTA1 0 3 HDSTA0 0 2 HDPW10 0 1 HDPW9 0 0 (LSB) HDPW8 0
*
HDSTA4~HDSTA0: Sets the HD output timing. This setting works in combination with the setting of HDSTA10~HDSTA5 in Sub-Address 05H. HDPW10~HDPW8: Sets the HD width. This setting works in combination with the setting of HDPW7 ~HDPW0 in Sub-Address 07H.
*
Sub-Address 07H
Bit Name Default 7 (MSB) HDPW7 1 6 HDPW6 0 5 HDPW5 0 4 HDPW4 0 3 HDPW3 0 2 HDPW2 0 1 HDPW1 0 0 (LSB) HDPW0 0
*
HDPW7~HDPW0: Sets the HD width. This setting works in combination with the setting of HDPW10 ~HDPW8 in Sub-Address 06H.
Sub-Address 08H
Bit Name Default 7 (MSB) IHVD 0 6 VRTMG9 1 5 VRTMG8 0 4 VRTMG7 0 3 VRTMG6 0 2 VRTMG5 0 1 VRTMG4 0 0 (LSB) VRTMG3 1
*
IHVD: Sets whether the I2C bus data is updated continuously or at the VD cycle. 0 (default): I2C bus data is updated continuously. 1: I2C bus data is updated at VD cycle.
*
VRTMG9~VRTMG3: Sets the number of lines per frame. Enabled only when VLINSEL in Sub-Address 00H = 1. This setting works in combination with the setting of VRTMG2~VRTMG0 in Sub-Address 09H.
19
2002-02-06
TC90A58F
Sub-Address 09H
Bit Name Default 7 (MSB) VRTMG2 1 6 VRTMG1 0 5 VRTMG0 0 4
VDOSELGT
3 VDOSEL 0
2 VGSTA 0
1 REGF1 0
0 (LSB) REGF2 0
0
*
VRTMG2~VRTMG0: Sets the number of lines per frame. Enabled only when VLINSEL in Sub-Address 00H = 1. This setting works in combination with VRTMG9~VRTMG3 in Sub-Address 08H. VDOSELGT: Selects VD after noise rejection by VGATE (VD gate pulse) or VDIN as the signal output to VDOUT. 0 (default): Outputs VDIN unchanged. 1: Outputs VD after noise rejection by VGATE.
*
*
VDOSEL: Selects VD generated by the internal V counter or VD selected by VDOSELGT as the signal output to VDOUT. 0 (default): Outputs VD selected by VDOSELGT. 1: Outputs VD generated by the internal V counter.
*
VGSTA: Selects the falling or rising edge of VDIN as the VGATE starting point. 0 (default): Selects falling edge of VDIN as the VGATE starting point. 1: Selects rising edge of VDIN as the VGATE starting point. Set to 0 if VDIN has positive polarity. Set to 1 if VDIN has negative polarity.
*
REGF1: Forces serial byte processing (alternately outputs color difference signal and Y signal as 8-bit data). 0 (default): Performs serial byte processing only in R656 and R601 8-Bit Modes. 1: Forces serial byte processing to be performed.
*
REGF2: Sets the data between EAV and SAV. 0 (default): Sets data between EAV and SAV to be 80H (Cb or Cr) or 10H (Y). 1: Does not set data between EAV and SAV but outputs the input data unchanged.
Sub-Address 0CH
Bit Name Default 7 (MSB) ADCLAPO 0 6 CLPSTA10 0 5 CLPSTA9 0 4 CLPSTA8 0 3 CLPSTA7 1 2 CLPSTA6 0 1 CLPSTA5 0 0 (LSB) CLPSTA4 1
*
ADCLAPO: Sets the polarity for clamp pulse. 0 (default): Inverts polarity. 1: Does not invert polarity.
*
CLPSTA10~CLPSTA4: Sets the starting point of the clamp pulse generated internally in Clamp Pulse Internal Generation Mode (i.e. when CLPSEL = 1 in Sub-Address 0EH). This setting works in combination with the setting of CLPSTA3~CLPSTA0 in Sub-Address 0DH.
20
2002-02-06
TC90A58F
Sub-Address 0DH
Bit Name Default 7 (MSB) CLPSTA3 0 6 CLPSTA2 0 5 CLPSTA1 0 4 CLPSTA0 0 3 CLPWID10 0 2 CLPWID9 0 1 CLPWID8 0 0 (LSB) CLPWID7 0
*
CLPSTA3~CLPSTA0: Sets the starting point of the clamp pulse generated internally in Clamp Pulse Internal Generation Mode (i.e. when CLPSEL = 1 in Sub-Address 0EH). This setting works in combination with the setting of CLPSTA10~CLPSTA4 in Sub-Address 06H. CLPWID10~CLPWID7: Sets the width of the clamp pulse generated internally in Clamp Pulse Internal Generation Mode (i.e. when CLPSEL = 1 in Sub-Address 0EH). This setting works in combination with the setting of CLPWID6~CLPWID0 in Sub-Address 0EH.
*
Sub-Address 0EH
Bit Name Default 7 (MSB) CLPWID6 1 6 CLPWID5 1 5 CLPWID4 0 4 CLPWID3 0 3 CLPWID2 0 2 CLPWID1 0 1 CLPWID0 0 0 (LSB) CLPSEL 0
*
CLPWID6~CLPWID0: Sets the width of the clamp pulse generated internally in Clamp Pulse Internal Generation Mode (i.e. when CLPSEL = 1 in Sub-Address 0EH). This setting works in combination with the setting of CLPWID10~CLPWID7 in Sub-Address 0DH. CLPSEL: Selects the externally input clamp pulse or internally generated clamp pulse. 0 (default): Externally input clamp pulse 1: Internally generated clamp pulse
*
Sub-Address 0FH
Bit Name Default 7 (MSB) 3/4 3/4 6 3/4 3/4 5 3/4 3/4 4 VGTEDA9 0 3 VGTEDA8 0 2 VGTEDA7 0 1 VGTEDA6 0 0 (LSB) VGTEDA5 0
*
VGTEDA9~VGTEDA5: Sets stop point 1 of VD-noise-rejected gate pulse. Enabled only when VGATEON in Sub-Address 11H = 1 This setting works in combination with the setting of VGTEDA4~VGTEDA0 in Sub-Address 10H.
Sub-Address 10H
Bit Name Default 7 (MSB) VGTEDA4 0 6 VGTEDA3 0 5 VGTEDA2 0 4 VGTEDA1 0 3 VGTEDA0 0 2 VGTEDB9 0 1 VGTEDB8 0 0 (LSB) VGTEDB7 0
*
VGTEDA4~VGTEDA0: Sets stop point 1 of VD-noise-rejected gate pulse. VGATEON = Enabled only when VGATEON in Sub-Address 11H = 1. This setting works in combination with the setting of VGTEDA9~VGTEDA5 in Sub-Address 0FH. VGTEDB9~VGTEDB7: Sets stop point 2 of VD-noise-rejected gate pulse. Enabled only when VGATEON in Sub-Address 11H = 1. This setting works in combination with the setting of VGTEDB6~VGTEDB0 in Sub-Address 11H.
*
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2002-02-06
TC90A58F
Sub-Address 11H
Bit Name Default 7 (MSB) VGTEDB6 0 6 VGTEDB5 0 5 VGTEDB4 0 4 VGTEDB3 0 3 VGTEDB2 0 2 VGTEDB1 0 1 VGTEDB0 0 0 (LSB) VGATEO 0
*
VGTEDB6~VGTEDB0: Sets stop point 2 of VD-noise-rejected gate pulse. Enabled only when VGATEON in Sub-Address 11H = 1. This setting works in combination with the setting of VGTEDB9~VGTEDB7 in Sub-Address 10H. VGATEON: Sets VD noise rejection ON/OFF. 0 (default): VD noise rejection OFF 1: VD noise rejection ON
*
Sub-Address 12H
Bit Name Default 7 (MSB) 3/4 3/4 6 ODEV10 0 5 ODEV9 0 4 ODEV8 0 3 ODEV7 0 2 ODEV6 0 1 ODEV5 0 0 (LSB) ODEV4 0
*
ODEV10~ODEV4: Sets the point (within 1H) where odd- or even-numbered field is identified. This setting works in combination with the setting of ODEV3~ODEV0 in Sub-Address 13H.
Sub-Address 13H
Bit Name Default 7 (MSB) ODEV3 0 6 ODEV2 0 5 ODEV1 0 4 ODEV0 0 3 ODDETPO 0 2 3/4 3/4 1 3/4 3/4 0 (LSB) 3/4 3/4
*
ODEV3~ODEV0: Sets the point (within 1H) where odd- or even-numbered field is identified. This setting works in combination with the setting of ODEV10~ODEV4 in Sub-Address 12H. ODDETPO: Sets polarity of pulse used to determine odd- or even-numbered field. 0 (default): Not inverted 1: Inverted
*
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2002-02-06
TC90A58F
Sub-Address 14H
Bit Name Default 7 (MSB) DIVIIC3 0 6 DIVIIC2 0 5 DIVIIC1 0 4 DIVIIC0 0 3 DIVHDSEL 0 2 HRESVAR 0 1 3/4 3/4 0 (LSB) 3/4 3/4
*
DIVIIC3~DIVIIC0: Switches the HPLL oscillation frequency. Enabled when CKSEL[3:0] (pins 72 to 75) are all set to 0. CKSEL[3:0] (pins 72 to 75) is enabled when DIVIIC3~DIVIIC0 is set to all 0s.
DIVIIC3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
DIVIIC2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
DIVIIC1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
DIVIIC0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
Clock Frequency 29.8 MHz 29.7 MHz 29.7 MHz 27 MHz 29.8 MHz 3/4 3/4 27 MHz 3/4 3/4 3/4 3/4 14.9 MHz 3/4 3/4 13.5 MHz
Horizontal Frequency 31.5 kHz, 480P 33.7 kHz, 1080I 45.0 kHz, 720P 31.5 kHz 15.7 kHz, 480I 3/4 3/4 15.7 kHz, general-purpose External clock input 3/4 3/4 3/4 15.7 kHz 3/4 3/4 15.7 kHz (Note6) (Note5)
For Note5 and Note6, the clocks are generated by dividing the main clock by 29.8 MHz and 27 MHz respectively. * DIVHDSEL: When using an internal HPLL, selects whether to use HDIN or the HPLL reference signal (generated internally) as HD in the logic block. 0 (default): Uses the HPLL reference signal (internally generated) as HD in the logic block. 1: Uses HDIN as HD in the logic block. * HRESVAR: Selects whether reset values for built-in H-counters are to be set internally or externally 0 (default): The reset values are set internally. 1: The reset values can be set externally.
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2002-02-06
TC90A58F
Sub-Address 17H
Bit Name Default 7 (MSB) REG4 0 6 REG5 0 5 REG6 0 4 REG10 0 3 YDLY3 0 2 YDLY2 0 1 YDLY1 0 0 (LSB) YDLY0 0
*
REG4: Sets the polarity of the control signal (CK2) for both Standard and Special 4:1:1 Modes. Changing the polarity enables the output order of Cb and Cr to be changed. 0 (default): Polarity is not inverted. For Standard 4:1:1 Mode: Outputs in the order (b7, b6), (b5, b4), (b3, b2), (b1, b0). For Special 4:1:1 Mode: Outputs in the order (b3, b2, b1, b0), (b7, b6, b5, b4). 1: Polarity is inverted. For Standard 4:1:1 Mode: Outputs in the order (b5, b4), (b7, b6), (b1, b0), (b3, b2). For Special 4:1:1 Mode: Outputs in the order (b7, b6, b5, b4), (b3, b2, b1, b0).
*
REG5: Sets the polarity of the control signal for serial byte (R656 or R601 8-Bit Mode) processing. Changing the polarity enables the output order of Cb (Cr) and Y to be changed. 0 (default): Polarity is not inverted. Outputs in the order Cb0, Y0, Cr0, Y1. 1: Polarity is inverted. Outputs in the order Y0, Cb0, Y1, Cr0.
*
REG6: Sets inversion/non-inversion of Cb and Cr MSB. 0 (default): Cb, Cr MSB is not inverted. Straight binary output 1: Cb, Cr MSB is inverted. Two's-complement output
*
REG10: Sets the polarity of the control signal for Standard 4:1:1 Mode and Standard and Special 4:2:2 Modes. 0 (default): Polarity is not inverted. For Standard 4:1:1 Mode: Outputs in the order (b7, b6), (b5, b4), (b3, b2), (b1, b0). For Standard and Special 4:2:2 Modes: Outputs in the order Cb, Cr, Cb, Cr. 1: The polarity is inverted. For standard 4:1:1 Mode: Outputs in the order (b3, b2), (b1, b0) (b7, b6), (b5, b4). For Standard and Special 4:2:2 Modes: Outputs in the order Cr, Cb, Cr, Cb.
*
YDLY3~YDLY0: Sets Y delay.
YDLY3 0 0 3/4 1 1 1
YDLY2 0 0 3/4 1 1 1
YDLY1 0 0 3/4 0 1 1
YDLY0 0 1 3/4 1 0 1 0 clocks 1 clock
Y Delay
13 clocks 14 clocks Invalid
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2002-02-06
TC90A58F
Sub-Address 18H
Bit Name Default 7 (MSB) REG11 0 6 LPFYPASS 0 5 LPI0ON2 0 4 LPI0ON1 0 3 LPI0ON0 0 2 LPQ0ON2 0 1 LPQ0ON 0 0 (LSB) LPQ0ON0 0
*
REG11: Sets the sampling point when down-sampling Y signal. 0 (default): Samples Y0, Y2 and Y4. 1: Samples Y1, Y3 and Y5.
*
LPFYPASS: Sets whether the Y signal passes or bypasses the LPF circuit. 0 (default): The Y signal passes through the LPF circuit. System delay (9 clocks) is added by the LPF circuit. 1: The Y signal bypasses the LPF circuit which adds a 1-clock delay.
*
LPI0ON2~LPI0ON0: Sets whether the Cb signal passes or bypasses the LPF circuit.
LPI0ON2 0 0 0 0 1 1 3/4 1
LPI0ON1 0 0 1 1 0 0 3/4 1
LPI0ON0 The Cb signal passes through the LPF circuit but is not filtered 0 (9-clock delay is added). 1 0 1 0 1 3/4 1 Invalid Filter ON (6 MHz) (9-clock delay is added) Invalid Filter ON (2.8 MHz) (9-clock delay is added) The Cb signal bypasses the LPF circuit (1-clock delay is added).
*
LPQ0ON2~LPQ0ON0: Sets whether the Cr signal passes or bypasses the LPF circuit.
LPQ0ON2 0 0 0 0 1 1 3/4 1
LPQ0ON1 0 0 1 1 0 0 3/4 1
LPQ0ON0 The Cb signal passes through the LPF circuit but the filter is not ON 0 (9-clock delay is added). 1 0 1 0 1 3/4 1 Invalid Filter ON (6 MHz) (9-clock delay is added) Invalid Filter ON (2.8 MHz) (9-clock delay is added) The Cb signal bypasses the LPF circuit (1-clock delay is added)
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2002-02-06
TC90A58F
Sub-Address 19H
Bit Name Default 7 (MSB) REG9 0 6 REG7 0 5 REG8 0 4 QDSEL1 0 3 QDSEL0 0 2 IDSEL1 0 1 IDSEL0 0 0 (LSB) LPYON 0
* *
REG9: Sets the polarity of the signal used to control Y signal down-sampling and the signal used to control the Cr signal down-sampling rate (down-sampling using 1/2 or 1/4 the main clock). 0 (default): Down-samples the Y signal only in R656 or R601 Modes. Down-samples the Cr signal only in R656, R601 or 4:1:1 Modes using 1/4 the main clock. 1: Down-samples the Y signal in all modes other than R656 or R601 Modes. Down-samples the Cr signal in all modes other than R656, R601, 4:4:4 or 4:1:1 Modes using 1/4 the main clock.
*
REG7: Enables/Disables QDSEL0 for the Cr signal. 0 (default): Disables QDSEL0. 1: Enables QDSEL0.
*
REG8: Enables/Disables QDSEL1 for the Cr signal. 0 (default): Disables QDSEL1. 1: Enables QDSEL1.
*
QDSEL [1:0]: Sets the sampling point for when the Cr signal is down-sampled.
Sampling Using 1/2 the Main Clock Cr0, Cr2, Cr4, ... Cr1, Cr3, Cr5, ... Unused Unused Sampling Using 1/4 the Main Clock Cr0, Cr4, Cr8, ... Cr1, Cr5, Cr9, ... Cr2, Cr6, Cr10, ... Cr3, Cr7, Cr11, ...
QDSEL1 0 0 1 1
QDSEL0 0 1 0 1
*
IDSEL1~IDSEL0: Sets the sampling point for when the Cb signal is down-sampled.
Sampling Using 1/2 the Main Clock Cb0, Cb2, Cb4, ... Cb1, Cb3, Cb5, ... Unused Unused Sampling Using 1/4 the Main Clock Cb0, Cb4, Cb8, ... Cb1, Cb5, Cb9, ... Cb2, Cb6, Cb10, ... Cb3, Cb7, Cb11, ...
IDSEL1 0 0 1 1
IDSEL0 0 1 0 1
*
LPYON: Turns the Y LPF ON/OFF. Enabled only when LPFYPASS in Sub-Address 18H = 0. 0 (default): Y LPF OFF 1: Y LPF ON (6 MHz)
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2002-02-06
TC90A58F
Sub-Address 1AH
Bit Name Default 7 (MSB) REG12 0 6 3/4 3/4 5 3/4 3/4 4 3/4 3/4 3 3/4 3/4 2 3/4 3/4 1 3/4 3/4 0 (LSB) 3/4 3/4
*
REG12: Sets inversion/non-inversion of the Y MSB. 0 (default): Does not invert the Y MSB. Straight binary output 1: Inverts the Y MSB. Two's-complement output
Sub-Address 1BH
Bit Name Default 7 (MSB) 6 5 4 3 2 REGSWB7 0 1 REGSWB6 0 0 (LSB) REGSWH 0
REGSWR7 REGSWR1 REGSWG7 REGSWG3 REGSWG1 0 0 0 0 0
*
REGSWR7: Forces ROUT[7:2] to Input Mode. 0 (default): Input and output settings depend on test mode. 1: Forces ROUT[7:2] to Input Mode.
*
REGSWR1: Forces ROUT[1:0] to Input Mode. 0 (default): Input and output settings depend on test mode. 1: Forces ROUT[1:0] to Input Mode.
*
REGSWG7: Forces GOUT[7:4] to High-Impedance. 0 (default): Output and High-Impedance settings depend on test mode. 1: Forces GOUT[7:4] to High-Impedance.
*
REGSWG3: Forces GOUT[3:2] to High-Impedance. 0 (default): Output and High-Impedance settings depend on test mode. 1: Forces GOUT[3:2] to High-Impedance.
*
REGSWG1: Forces GOUT[1:0] to High-Impedance. 0 (default): Output and High-Impedance settings depend on test mode. 1: Forces GOUT[1:0] to High-Impedance.
*
REGSWB7: Forces BOUT7 to High-Impedance. 0 (default): Output and High-Impedance settings depend on test mode. 1: Forces BOUT7 to High-Impedance.
*
REGSWG6: Forces BOUT6~BOUT0 to High-Impedance. 0 (default): Output and High-Impedance settings depend on test mode. 1: Forces BOUT[6:0] to High-Impedance.
*
REGSWHV: Forces HDOUT and VDOUT to Input Mode. 0 (default): Input and output settings depend on test mode. 1: Forces HDOUT and VDOUT to Input Mode.
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2002-02-06
TC90A58F
Sub-Address 1CH
Bit Name Default 7 (MSB) M10B 0 6 3/4 3/4 5 3/4 3/4 4
CKOUTSTP
3 3/4 3/4
2 3/4 3/4
1 3/4 3/4
0 (LSB) 3/4 3/4
0
*
M10B: Sets 10-Bit Output Mode. Note that only two channels, Y ADC and Cb ADC, can be set to 10-Bit Output Mode. 0 (default): 8-Bit Output Mode for all three channels 1: 10-Bit Output Mode for two channels (Y and Cb)
*
CKOUTSTP: Turns CKOUT output ON/OFF. 0 (default): CKOUT output ON 1: CKOUT output OFF. The output is High-Impedance.
Sub-Address 2AH
Bit Name Default 7 (MSB) 3/4 3/4 6 3/4 3/4 5 3/4 3/4 4 3/4 3/4 3 3/4 3/4 2 3/4 3/4 1 BAR 0 0 (LSB) 3/4 3/4
*
BAR: Sets Y, Cb and Cr signal output to internal color bar signal output (for testing purposes). 0 (default): Normal operating mode 1: Sets Y, Cb and Cr signal output to internal color bar signal output.
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2002-02-06
TC90A58F
Maximum Ratings (Ta = 25C)
Characteristics Power supply voltage Input voltage Power dissipation Storage temperature Symbol VDD VIN PD Tstg Rating VSS to VSS + 4.5 -0.3 to VDD + 0.3 1923 -55 to 125 Unit V V mW C
Ta-PD (4-layer board mounting)
Power dissipation
(mW)
1923
962
25
75
125
Ambient temperature (C)
Recommended Operating Conditions
Characteristics Power supply voltage Input voltage Operating temperature Symbol VDD VIN Topr Min 3.0 0 -20 Typ. 3.3 3/4 3/4 Max 3.6 VDD 70 Unit V V C
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2002-02-06
TC90A58F
DC Characteristics
Characteristics Current Dissipation High-level input voltage Low-level input voltage Input current Low-level High-level Output voltage Low-level CMOS Schmitt CMOS Schmitt High-level VIL IIH IIL VOH VOL VIH Symbol IDD Test Circuit 3/4 3/4 Test Condition 3/4 3/4 3/4 3/4 3/4 VIN = VDD VIN = VSS IOH = 4 mA IOH = -4 mA 2.4 2.65 3/4 3/4 -10 -10 2.4 3/4 Min Typ. 200 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 Max 3/4 3/4 3/4 0.9 V 0.65 10 A 10 3/4 0.4 V Unit mA V
3/4 3/4 3/4 3/4 3/4
AC Characteristics
Characteristics Operating frequency condition Input set-up time Input hold time Symbol Fclk ts th Test Circuit 3/4 3/4 3/4 Test Condition 3/4 EXTCLK reference EXTCLK reference Min 3/4 1 7 Typ. 3/4 3/4 3/4 Max 30 3/4 3/4 Unit MHz ns ns Notes 3/4 3/4 3/4 CKPOL = 0 Clock data output phase difference 1 tdata1 3/4 EXTCLK input Output load = 30 pF 0 3/4 9 ns (CKOUT output and internal clock have Same polarity.) CKPOL = 0 Clock data output phase difference 2 tdata2 3/4 EXTCLK input Output load = 30 pF 0 3/4 7 ns (CKOUT output and internal clock have Same polarity.) CKPOL = 1 EXTCLK input Clock data output phase difference 3 tdata3 3/4 Duty = 50%, Output load = 30 pF -18 3/4 -9 ns (CKOUT output and internal clock have Opposite polarity.) CKPOL = 1 EXTCLK input, Clock data output phase difference 4 tdata4 3/4 Duty = 50%, Output load = 30 pF -18 3/4 -10 ns (CKOUT output and internal clock have Opposite polarity.) CKPOL = 0 Output signal delay time 1 tpd1 3/4 3/4 6 3/4 17 ns (CKOUT output and internal clock have Same polarity.) CKPOL = 1 Output signal delay time 2 tpd2 3/4 3/4 23 3/4 35 ns (CKOUT output and internal clock have Opposite polarity.) 3/4 3/4
Output signal delay time 3 Output signal delay time 4
tpd3 tpd4
3/4 3/4
3/4 3/4
8 8
3/4 3/4
23 22
ns ns
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2002-02-06
TC90A58F
EXTCLK
Data (HDIN, VDIN, CLAMP) ts th
Figure 6 Data Set-up Hold Time
(1) Same polarity output of CKOUT (CKPOL = 0, default, set by I2C bus register)
CKOUT
Data (ROUT, BOUT, GOUT)
tdata1 = 0 ns (min)~9 ns (max)
CKOUT
Data (HDOUT, VDOUT) tdata2 tdata2 = 0 ns (min)~7 ns (max)
(2)
Inverted-polarity output of CKOUT (CKPOL = 1, clock duty = 50%, set by I2C bus register)
CKOUT
Data (ROUT, BOUT, GOUT) tdata3 tdata3 = -18 ns (min)~-9 ns (max)
CKOUT
Data (HDOUT, VDOUT) tdata4 tdata4 = -18 ns (min)~-10 ns (max)
Figure 7 Phase Difference between Clock and Data Output
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2002-02-06
TC90A58F
(1) Same polarity output of CKOUT (CKPOL = 0, default, set by I2C bus register)
EXTCLK
CKOUT
tpd1
(2)
Inverted-polarity output of CKOUT (CKPOL = 1, set by I2C bus register)
EXTCLK
CKOUT
tpd2
EXTCLK
Data (ROUT, BOUT, GOUT) tpd3
EXTCLK
Data (HDOUT, VDOUT) tpd4
Figure 8 Output Signal Delay Time
Note7: When the clock duty (TC90A58F internal clock duty) changes, the output signal delay times tpd3 and tpd4 (when CKPOL = 1) change only by CKOUT output delay. Thus, the phase difference between CKOUT and the data changes by the change in the CKOUT output delay. The TC90A58F internal clock is the output from the CKOUT pin when CKPOL = 0 (default).
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TC90A58F
Electrical Characteristics of ADC Block (fclk = 30 MHz, AVDD = 3.3 V, Ta = 25C)
Characteristics Input voltage level Conversion speed Analog input band Differential non-linear error Integral non-linear error Symbol VAD fclk BW ED EL
in
Test Circuit 3/4 3/4 3/4 3/4 3/4
Test Condition 3/4 3/4 80% amplitude input -1dB 3/4 3/4
Min 3/4 3/4 3/4 3/4 3/4 Theoretical value -10 Theoretical value -50
Typ. 1.32 3/4 10 1.5 4 3/4 3/4 3/4 3/4 6.5
Max 3/4 30 3/4 3/4 3/4 Theoretical value +50 Theoretical value +10 3/4
Unit Vp-p MHz MHz LSB LSB
Note 3/4 3/4 3/4 10-bit conversion value 10-bit conversion value VDD 0.3
Zero-scale error
Vzd
3/4
3/4
mV
(zero-scale theoretical value)
VDD 0.7 mV (full-scale theoretical value)
Full-scale error
Vfd
3/4
3/4
Input capacity
Cin
3/4
3/4
3/4
pF
3/4
Electrical Characteristics of HPLL Block
Characteristics Output frequency range Symbol fu Test Circuit 3/4 Test Condition 3/4 Min 27 Typ. 3/4 8
(Note8)
Max 29.82
Unit MHz
Note See table below (Note9)
480i mode Jitter tjit 3/4 720p mode
3/4
3/4 ns 3/4
3/4
6
(Note8)
3/4
Note8: The jitter value depends to a large extent on the circuit layout on the board and the constants for the external circuits. It is also affected by external devices. Take care when designing the pattern for the board. Note9: Oscillation frequencies for each screen mode are as listed below.
Oscillation Frequency 29.82 MHz 29.82 MHz 29.7 MHz 29.7 MHz 27 MHz 27 MHz
Screen Mode 480i 480p 1080i 720p R656, R601 (NTSC) R656, R601 (PAL)
fH (kHz) 15.75 31.5 33.7 45 15.734 15.625
Times 1896 948 880 660 1716 1728
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TC90A58F
Application Circuit Example
0.1 mF 8.2 kW
0.47 mF 20 W
0.1 mF 0.1 mF
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 CKSEL1 CKSEL2 CKSEL3 RREF VRT_Y AVSS AIN_Y AVDD VRB_Y VRM_Y DVSSA DVDDA DVSS 0.1 mF 0.1 mF 0.1 mF 0.47 mF 20 W 0.1 F 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 TES1 TES2 CLAMP RESN CKSEL0 DVDD TES0 BIAS VRM_I VRB_I AVDD AIN_I AVSS VRT_I DACOUT VB1 VRM_Q VRB_Q AVDD AIN_Q AVSS VRT_Q PVDD APCLK PVSS LFIL BFIL
0.1 mF 0.1 mF 0.1 mF 0.47 mF 20 W 0.1 mF 0.01 mF 1 mF 1.0 kW
TC90A58F
DVDDP EXTCLK DVSSP HDIN VDIN HREF SDA SCL VDOUT HDOUT DVDD DVSS BOUT0
0.01 mF
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
BOUT1 BOUT2 BOUT3 BOUT4 BOUT5 BOUT6 BOUT7
ROUT7 ROUT6 ROUT5 ROUT4 ROUT3 ROUT2 ROUT1 ROUT0 DVSS GOUT7 GOUT6 GOUT5 GOUT4 GOUT3 GOUT2 GOUT1 GOUT0 DVSS CKOUT DVDD
60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41
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TC90A58F
Package Dimensions
Weight:
g (typ.)
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TC90A58F
RESTRICTIONS ON PRODUCT USE
000707EBA
* TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the "Handling Guide for Semiconductor Devices," or "TOSHIBA Semiconductor Reliability Handbook" etc.. * The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These TOSHIBA products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury ("Unintended Usage"). Unintended Usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA products listed in this document shall be made at the customer's own risk. * The products described in this document are subject to the foreign exchange and foreign trade laws. * The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA CORPORATION for any infringements of intellectual property or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any intellectual property or other rights of TOSHIBA CORPORATION or others. * The information contained herein is subject to change without notice.
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2002-02-06

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